Digital Electronics (4321102) - Summer 2023 Solution

Question 1(a) [3 marks]

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Explain De-Morgan’s theorem for Boolean algebra

Answer: De-Morgan’s theorem consists of two laws that show the relationship between AND, OR, and NOT operations:

Law 1: The complement of a sum equals the product of complements $\overline{A + B} = \overline{A} \cdot \overline{B}$

Law 2: The complement of a product equals the sum of complements $\overline{A \cdot B} = \overline{A} + \overline{B}$

Table: De-Morgan’s Laws Verification

Mnemonic: “NOT over OR becomes AND of NOTs, NOT over AND becomes OR of NOTs”

Question 1(b) [4 marks]

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Convert following decimal number into binary and octal number (i) 215 (ii) 59

Answer:

Binary Conversion:

For 215:

• Divide by 2 repeatedly: 215/2 = 107 remainder 1
• 107/2 = 53 remainder 1
• 53/2 = 26 remainder 1
• 26/2 = 13 remainder 0
• 13/2 = 6 remainder 1
• 6/2 = 3 remainder 0
• 3/2 = 1 remainder 1
• 1/2 = 0 remainder 1
• Therefore, (215)₁₀ = (11010111)₂

For 59:

• Divide by 2 repeatedly: 59/2 = 29 remainder 1
• 29/2 = 14 remainder 1
• 14/2 = 7 remainder 0
• 7/2 = 3 remainder 1
• 3/2 = 1 remainder 1
• 1/2 = 0 remainder 1
• Therefore, (59)₁₀ = (111011)₂

Octal Conversion:

For 215:

• Divide by 8 repeatedly: 215/8 = 26 remainder 7
• 26/8 = 3 remainder 2
• 3/8 = 0 remainder 3
• Therefore, (215)₁₀ = (327)₈

For 59:

• Divide by 8 repeatedly: 59/8 = 7 remainder 3
• 7/8 = 0 remainder 7
• Therefore, (59)₁₀ = (73)₈

Table: Number Conversion Summary

Mnemonic: “Divide by base, read remainders bottom-up”

Question 1(c)(I) [2 marks]

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Write the base of decimal, binary, octal and hexadecimal number system

Answer:

Table: Number System Bases

Mnemonic: “D-B-O-H: 10-2-8-16”

Question 1(c)(II) [2 marks]

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(147)₁₀ = ()₂ = (__)₁₆

Answer:

Decimal to Binary conversion:

• 147/2 = 73 remainder 1
• 73/2 = 36 remainder 1
• 36/2 = 18 remainder 0
• 18/2 = 9 remainder 0
• 9/2 = 4 remainder 1
• 4/2 = 2 remainder 0
• 2/2 = 1 remainder 0
• 1/2 = 0 remainder 1
• Therefore, (147)₁₀ = (10010011)₂

Decimal to Hexadecimal conversion:

• Group binary digits in sets of 4: 1001 0011
• Convert each group to hex: 1001 = 9, 0011 = 3
• Therefore, (147)₁₀ = (93)₁₆

Table: Conversion Result

Mnemonic: “Group by 4 from right for hex”

Question 1(c)(III) [3 marks]

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Convert following binary code into grey code (i) 1011 (ii) 1110

Answer:

Binary to Gray code conversion procedure:

1. The MSB (leftmost bit) of the Gray code is the same as the MSB of the binary code
2. Other bits of the Gray code are obtained by XORing adjacent bits of the binary code

For 1011:

• MSB of Gray = MSB of Binary = 1
• Second bit = 1 XOR 0 = 1
• Third bit = 0 XOR 1 = 1
• Fourth bit = 1 XOR 1 = 0
• Therefore, (1011)₂ = (1110)ᵍᵣₐᵧ

For 1110:

• MSB of Gray = MSB of Binary = 1
• Second bit = 1 XOR 1 = 0
• Third bit = 1 XOR 1 = 0
• Fourth bit = 1 XOR 0 = 1
• Therefore, (1110)₂ = (1001)ᵍᵣₐᵧ

Table: Binary to Gray Code Conversion

Mnemonic: “Keep first, XOR the rest”

Question 1(c) [OR Question] (I) [2 marks]

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Write the full form of BCD and ASCII

Answer:

Table: Full Forms of BCD and ASCII

Mnemonic: “Binary Codes Decimal values, American Standards Code Information”

Question 1(c) [OR Question] (II) [2 marks]

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Write 1’s and 2’s complement of following binary numbers: (i) 1010 (ii) 1011

Answer:

1’s Complement: Invert all bits (change 0 to 1 and 1 to 0) 2’s Complement: Take 1’s complement and add 1

For 1010:

• 1’s complement: 0101
• 2’s complement: 0101 + 1 = 0110

For 1011:

• 1’s complement: 0100
• 2’s complement: 0100 + 1 = 0101

Table: Complement Results

Mnemonic: “Flip all bits for 1’s, Add one more for 2’s”

Question 1(c) [OR Question] (III) [3 marks]

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Perform subtraction using 2’s complement method (i) (110110)₂ – (101010)₂

Answer:

To subtract using 2’s complement method:

1. Find 2’s complement of subtrahend
2. Add it to the minuend
3. Discard any carry beyond the bit width

Subtraction: (110110)₂ – (101010)₂

Step 1: Find 2’s complement of 101010

• 1’s complement of 101010 = 010101
• 2’s complement = 010101 + 1 = 010110

Step 2: Add 110110 + 010110

  1 1 1 1 1
  1 1 0 1 1 0
+ 0 1 0 1 1 0
--------------
  0 0 1 1 0 0

Step 3: Result is 001100 = (12)₁₀

Table: Subtraction Process

Mnemonic: “Complement the subtracted, add them up, carry goes away”

Question 2(a) [3 marks]

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Draw logic circuit of AND, OR and NOT gate using NAND gate only

Answer:

AND gate using NAND gates:

• AND gate = NAND gate followed by NOT gate (NAND gate)

OR gate using NAND gates:

• OR gate = Apply NOT (NAND gate) to both inputs, then NAND those results

NOT gate using NAND gate:

• NOT gate = NAND gate with both inputs tied together

graph LR
  subgraph "NOT Gate"
    A1[A] --> NAND1([NAND])
    A1 --> NAND1
    NAND1 --> notA[NOT A]
  end
  
  subgraph "AND Gate"
    B1[B] --> NAND2([NAND])
    C1[C] --> NAND2
    NAND2 --> NAND3([NAND])
    NAND2 --> NAND3
    NAND3 --> andResult[B AND C]
  end
  
  subgraph "OR Gate"
    D1[D] --> NAND4([NAND])
    D1 --> NAND4
    E1[E] --> NAND5([NAND])
    E1 --> NAND5
    NAND4 --> NAND6([NAND])
    NAND5 --> NAND6
    NAND6 --> orResult[D OR E]
  end

Mnemonic: “NAND alone for NOT, NAND twice for AND, NAND each then NAND again for OR”

Question 2(b) [4 marks]

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Draw/Write logic symbol, truth table and equation of following logic gates (i) XOR gate (ii) OR gate

Answer:

XOR Gate:

Logic Symbol:

graph LR
    A[A] --> XOR([⊕])
    B[B] --> XOR
    XOR --> Y[Y]

Truth Table:

Boolean Equation: Y = A⊕B = A’B + AB'

OR Gate:

Logic Symbol:

graph LR
    A[A] --> OR([≥1])
    B[B] --> OR
    OR --> Y[Y]

Truth Table:

Boolean Equation: Y = A+B

Mnemonic: “XOR: Exclusive OR - one or the other but not both; OR: one or the other or both”

Question 2(c)(I) [3 marks]

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Simplify the Boolean expression using algebraic method Y = A + B[AC + (B + C̅)D]

Answer:

Step-by-step simplification:

Y = A + B[AC + (B + C̅)D] Y = A + B[AC + BD + C̅D] Y = A + BAC + BBD + BC̅D Y = A + BAC + BD + BC̅D (Since BB = B)

Apply absorption law (X + XY = X): Y = A + AC + BD + BC̅D (Since A + BAC = A + AC) Y = A + BD + BC̅D (Since A + AC = A) Y = A + B(D + C̅D) Y = A + BD + BC̅D Y = A + BD(1 + C̅) Y = A + BD (Since 1 + C̅ = 1)

Final expression: Y = A + BD

Table: Simplification Steps

Mnemonic: “Always look for idempotence, absorption, and complement patterns”

Question 2(c)(II) [4 marks]

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Simplify the Boolean expression using Karnaugh Map F(A,B,C) = Σm(0, 2, 3, 4, 5, 6)

Answer:

Create K-map for F(A,B,C) = Σm(0, 2, 3, 4, 5, 6):

K-map:

    BC
   00 01 11 10
A 0| 1  0  0  1
  1| 1  1  0  1

Group the 1s:

• Group 1: m(0,4) - corresponds to A’B’C'
• Group 2: m(2,6) - corresponds to B’C
• Group 3: m(4,5) - corresponds to AB'

Simplified expression: F(A,B,C) = B’C + A’B’C’ + AB'

Let’s simplify further: F(A,B,C) = B’C + B’C’(A’ + A) F(A,B,C) = B’C + B’C' F(A,B,C) = B’(C + C’) F(A,B,C) = B'

Final expression: F(A,B,C) = B'

Diagram: K-map grouping

    BC
   00 01 11 10
A 0| 1  0  0  1
  1| 1  1  0  1
    ↑_____↑  ↑_____↑
       │        │
    Group 1   Group 2
    
    ↑______↑
    │  
 Group 3

Mnemonic: “Group adjacent 1s in powers of 2”

Question 2 [OR Question] (a) [3 marks]

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Draw logic circuit of AND, OR and NOT gate using NOR gate only

Answer:

NOT gate using NOR gate:

• NOT gate = NOR gate with both inputs tied together

AND gate using NOR gates:

• AND gate = Apply NOT (NOR gate) to both inputs, then NOR those results again

OR gate using NOR gates:

• OR gate = NOR gate followed by NOT gate (NOR gate)

graph LR
  subgraph "NOT Gate"
    A1[A] --> NOR1([NOR])
    A1 --> NOR1
    NOR1 --> notA[NOT A]
  end
  
  subgraph "AND Gate"
    B1[B] --> NOR2([NOR])
    B1 --> NOR2
    C1[C] --> NOR3([NOR])
    C1 --> NOR3
    NOR2 --> NOR4([NOR])
    NOR3 --> NOR4
    NOR4 --> andResult[B AND C]
  end
  
  subgraph "OR Gate"
    D1[D] --> NOR5([NOR])
    E1[E] --> NOR5
    NOR5 --> NOR6([NOR])
    NOR5 --> NOR6
    NOR6 --> orResult[D OR E]
  end

Mnemonic: “NOR alone for NOT, NOT each then NOR for AND, Double NOR for OR”

Question 2 [OR Question] (b) [4 marks]

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Draw/Write logic symbol, truth table and equation of following logic gates (i) NOR gate (ii) AND gate

Answer:

NOR Gate:

Logic Symbol:

graph LR
    A[A] --> NOR([≥1 with bubble])
    B[B] --> NOR
    NOR --> Y[Y]

Truth Table:

Boolean Equation: Y = (A+B)’ = A’B'

AND Gate:

Logic Symbol:

graph LR
    A[A] --> AND([&])
    B[B] --> AND
    AND --> Y[Y]

Truth Table:

Boolean Equation: Y = A·B

Mnemonic: “NOR: NOT OR - neither one nor the other; AND: both must be 1”

Question 2 [OR Question] (c) [7 marks]

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Write the Boolean expression of Q for above logic circuit. Simplify the Boolean expression of Q and draw the logic circuit of simplified circuit using AND-OR-Invert method

Answer:

Step 1: Write Boolean expression from the circuit: Q = (A + B) · (B + C · ((B + C)’)) Q = (A + B) · (B + C · (B’ · C’)) Q = (A + B) · (B + C · B’ · C')

Step 2: Simplify the expression:

• Note that C · C’ = 0
• Therefore, C · B’ · C’ = 0
• So Q = (A + B) · (B + 0) = (A + B) · B = A·B + B·B = A·B + B = B + A·B = B(1 + A) = B

Step 3: Final simplified expression: Q = B

Step 4: AND-OR-Invert implementation of Q = B:

• This is simply a wire from input B to output Q

graph LR
    B[B] --> Q[Q]

Table: Simplification Steps

Mnemonic: “When complementary variables multiply, they zero out”

Question 3(a) [3 marks]

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Define combinational circuit. Give two examples of combinational circuits

Answer:

Combinational circuit: A digital circuit whose output depends only on the current input values and not on previous inputs or states. In combinational circuits, there is no memory or feedback.

Key characteristics:

• Output depends only on current inputs
• No memory elements
• No feedback paths

Examples of combinational circuits:

1. Multiplexers (MUX)
2. Decoders
3. Adders/Subtractors
4. Encoders
5. Comparators

Table: Combinational vs Sequential Circuits

Mnemonic: “Combinational circuits: Current In, Current Out - no memory about”

Question 3(b) [4 marks]

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Explain half adder using logic circuit and truth table

Answer:

Half Adder: A combinational circuit that adds two binary digits and produces sum and carry outputs.

Logic Circuit:

graph LR
    A[A] --> XOR([⊕])
    B[B] --> XOR
    XOR --> S[Sum]
    A --> AND([&])
    B --> AND
    AND --> C[Carry]

Truth Table:

Boolean Equations:

• Sum = A ⊕ B = A’B + AB'
• Carry = A · B

Limitations:

• Cannot add three binary digits
• Cannot accommodate carry input from previous stage

Mnemonic: “XOR for Sum, AND for Carry”

Question 3(c)(I) [3 marks]

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Explain multiplexer in brief

Answer:

Multiplexer (MUX): A combinational circuit that selects one of several input signals and forwards it to a single output line based on select lines.

Key features:

• Acts as a digital switch
• Has 2ⁿ data inputs, n select lines, and 1 output
• Select lines determine which input is connected to output

Common multiplexers:

• 2:1 MUX (1 select line)
• 4:1 MUX (2 select lines)
• 8:1 MUX (3 select lines)

Basic structure:

graph LR
    I0[I0] --> MUX([MUX])
    I1[I1] --> MUX
    In[...] --> MUX
    I2n-1[I2^n-1] --> MUX
    S[Select Lines] --> MUX
    MUX --> Y[Output Y]

Applications:

• Data routing
• Data selection
• Parallel to serial conversion
• Implementation of Boolean functions

Mnemonic: “Many In, Selection picks, One Out”

Question 3(c)(II) [4 marks]

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Design 8:1 multiplexer. Write its truth table and draw its logic circuit

Answer:

8:1 Multiplexer Design:

• 8 data inputs (I₀ to I₇)
• 3 select lines (S₂, S₁, S₀)
• 1 output (Y)

Truth Table:

Boolean Equation: Y = S₂’·S₁’·S₀’·I₀ + S₂’·S₁’·S₀·I₁ + S₂’·S₁·S₀’·I₂ + S₂’·S₁·S₀·I₃ + S₂·S₁’·S₀’·I₄ + S₂·S₁’·S₀·I₅ + S₂·S₁·S₀’·I₆ + S₂·S₁·S₀·I₇

Logic Circuit:

graph TD
    I0[I0] --> AND0([&])
    I1[I1] --> AND1([&])
    I2[I2] --> AND2([&])
    I3[I3] --> AND3([&])
    I4[I4] --> AND4([&])
    I5[I5] --> AND5([&])
    I6[I6] --> AND6([&])
    I7[I7] --> AND7([&])

    S0n["S0'"] --> AND0
    S1n["S1'"] --> AND0
    S2n["S2'"] --> AND0
    
    S0["S0"] --> AND1
    S1n --> AND1
    S2n --> AND1
    
    S0n --> AND2
    S1["S1"] --> AND2
    S2n --> AND2
    
    S0 --> AND3
    S1 --> AND3
    S2n --> AND3
    
    S0n --> AND4
    S1n --> AND4
    S2["S2"] --> AND4
    
    S0 --> AND5
    S1n --> AND5
    S2 --> AND5
    
    S0n --> AND6
    S1 --> AND6
    S2 --> AND6
    
    S0 --> AND7
    S1 --> AND7
    S2 --> AND7
    
    AND0 --> OR([≥1])
    AND1 --> OR
    AND2 --> OR
    AND3 --> OR
    AND4 --> OR
    AND5 --> OR
    AND6 --> OR
    AND7 --> OR
    
    OR --> Y[Y]

Mnemonic: “Eight inputs, three selects, decode and OR to output”

Question 3 [OR Question] (a) [3 marks]

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Draw the block diagram of 4-bit binary parallel adder

Answer:

4-bit Binary Parallel Adder: A circuit that adds two 4-bit binary numbers and produces a 4-bit sum and a carry output.

graph LR
    A0[A0] --> FA0[FA]
    B0[B0] --> FA0
    Cin[Cin=0] --> FA0
    FA0 --> S0[S0]

    A1[A1] --> FA1[FA]
    B1[B1] --> FA1
    FA0 --C1--> FA1
    FA1 --> S1[S1]
    
    A2[A2] --> FA2[FA]
    B2[B2] --> FA2
    FA1 --C2--> FA2
    FA2 --> S2[S2]
    
    A3[A3] --> FA3[FA]
    B3[B3] --> FA3
    FA2 --C3--> FA3
    FA3 --> S3[S3]
    
    FA3 --C4--> Cout[Cout]

Components:

• Four full adders (FA) connected in cascade
• Each FA adds corresponding bits and the carry from previous stage
• Initial carry-in (Cin) is typically 0

Mnemonic: “Four FAs linked, carries ripple through”

Question 3 [OR Question] (b) [4 marks]

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Explain full adder using logic circuit and truth table

Answer:

Full Adder: A combinational circuit that adds three binary digits (two inputs and a carry-in) and produces sum and carry outputs.

Logic Circuit:

graph TD
    A[A] --> XOR1([⊕])
    B[B] --> XOR1
    XOR1 --> XOR2([⊕])
    Cin[Cin] --> XOR2
    XOR2 --> Sum[Sum]

    A --> AND1([&])
    B --> AND1
    XOR1 --> AND2([&])
    Cin --> AND2
    AND1 --> OR([≥1])
    AND2 --> OR
    OR --> Cout[Carry out]

Truth Table:

Boolean Equations:

• Sum = A ⊕ B ⊕ Cin
• Cout = A·B + (A⊕B)·Cin

Mnemonic: “XOR all three for Sum, OR the ANDs for Carry”

Question 3 [OR Question] (c) (I) [3 marks]

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Explain 4:1 multiplexer using logic circuit and truth table

Answer:

4:1 Multiplexer: A digital switch that selects one of four input lines and connects it to the output based on two select lines.

Logic Circuit:

graph TD
    I0[I0] --> AND0([&])
    I1[I1] --> AND1([&])
    I2[I2] --> AND2([&])
    I3[I3] --> AND3([&])

    S0n["S0'"] --> AND0
    S1n["S1'"] --> AND0
    
    S0["S0"] --> AND1
    S1n --> AND1
    
    S0n --> AND2
    S1["S1"] --> AND2
    
    S0 --> AND3
    S1 --> AND3
    
    AND0 --> OR([≥1])
    AND1 --> OR
    AND2 --> OR
    AND3 --> OR
    
    OR --> Y[Y]

Truth Table:

Boolean Equation: Y = S1’·S0’·I0 + S1’·S0·I1 + S1·S0’·I2 + S1·S0·I3

Mnemonic: “Two select lines choose one of four inputs”

Question 3 [OR Question] (c) (II) [4 marks]

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Design 8:1 multiplexer using two 4:1 multiplexer.

Answer:

Design approach: Use two 4:1 MUXes and one 2:1 MUX to create an 8:1 MUX.

1. First 4:1 MUX handles inputs I0-I3 using select lines S0,S1
2. Second 4:1 MUX handles inputs I4-I7 using select lines S0,S1
3. 2:1 MUX selects between outputs of the two 4:1 MUXes using S2

Block Diagram:

graph TD
    I0[I0] --> MUX1([4:1 MUX])
    I1[I1] --> MUX1
    I2[I2] --> MUX1
    I3[I3] --> MUX1

    I4[I4] --> MUX2([4:1 MUX])
    I5[I5] --> MUX2
    I6[I6] --> MUX2
    I7[I7] --> MUX2
    
    S0[S0] --> MUX1
    S1[S1] --> MUX1
    S0 --> MUX2
    S1 --> MUX2
    
    MUX1 --> MUX3([2:1 MUX])
    MUX2 --> MUX3
    S2[S2] --> MUX3
    
    MUX3 --> Y[Y]

Truth Table:

Mnemonic: “S0,S1 select from each 4:1 MUX, S2 selects between them”

Question 4(a) [3 marks]

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Define sequential circuit. Give two examples of it

Answer:

Sequential Circuit: A digital circuit whose output depends not only on the current inputs but also on the past sequence of inputs (history/previous states).

Key characteristics:

• Contains memory elements (flip-flops)
• Output depends on both current inputs and previous states
• Usually incorporates feedback paths
• Requires clock signals for synchronization (for synchronous circuits)

Examples of sequential circuits:

1. Flip-flops (SR, JK, D, T)
2. Registers (shift registers)
3. Counters (binary, decade, ring counters)
4. State machines
5. Memory units

Table: Sequential vs Combinational Circuits

Mnemonic: “Sequential remembers history, combinational only knows now”

Question 4(b) [4 marks]

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Design decade counter

Answer:

Decade Counter: A sequential circuit that counts from 0 to 9 (decimal) and then resets to 0.

Design using JK flip-flops:

• Requires 4 JK flip-flops (Q3,Q2,Q1,Q0) to represent 4-bit binary number
• Counts from 0000 to 1001 (0-9 decimal) then resets

State Table:

Block Diagram:

graph LR
    CLK[Clock] --> FF0[JK0]
    CLK --> FF1[JK1]
    CLK --> FF2[JK2]
    CLK --> FF3[JK3]

    AND([&]) --> R[Reset]
    Q1 --> AND
    Q3 --> AND
    R --> FF0
    R --> FF1
    R --> FF2
    R --> FF3
    
    FF0 --Q0--> Q0[Q0]
    FF1 --Q1--> Q1[Q1]
    FF2 --Q2--> Q2[Q2]
    FF3 --Q3--> Q3[Q3]
    
    FF0 --Q0--> FF1
    FF1 --Q1--> FF2
    FF2 --Q2--> FF3

J-K Input Equations:

• J0 = K0 = 1 (toggle on every clock)
• J1 = K1 = Q0
• J2 = K2 = Q1·Q0
• J3 = K3 = Q2·Q1·Q0

Reset condition: When Q3·Q1 = 1 (state 1010), reset all flip-flops

Mnemonic: “Count BCD, reset after 9”

Question 4(c)(I) [3 marks]

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Explain S-R flip-flop using NOR gate. Draw its logic symbol and write its truth table.

Answer:

S-R Flip-flop using NOR gates: A basic flip-flop constructed from two cross-coupled NOR gates that can store one bit of information.

Logic Circuit:

graph TD
    S[S] --> NOR1([≥1])
    NOR2 --Q'--> NOR1

    R[R] --> NOR2([≥1])
    NOR1 --Q--> NOR2
    
    NOR1 --Q--> Q[Q]
    NOR2 --Q'--> Qn[Q']

Logic Symbol:

graph LR
    S[S] --> SR[SR]
    R[R] --> SR
    SR --Q--> Q[Q]
    SR --Q'--> Qn[Q']

Truth Table:

Mnemonic: “S sets to 1, R resets to 0, both active gives invalid state”

Question 4(c)(II) [4 marks]

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Explain S-R flip-flop using NAND gate. Write the limitation of SR flip flop

Answer:

S-R Flip-flop using NAND gates: A basic flip-flop constructed from two cross-coupled NAND gates.

Logic Circuit:

graph TD
    S[S] --> NAND1([&])
    NAND2 --Q--> NAND1

    R[R] --> NAND2([&])
    NAND1 --Q'--> NAND2
    
    NAND1 --Q'--> Qn[Q']
    NAND2 --Q--> Q[Q]

Truth Table:

Limitations of SR Flip-flop:

1. Invalid state: When both S=1, R=1 (for NOR) or S=0, R=0 (for NAND), the output is unpredictable
2. Race condition: When inputs change simultaneously, the final state can be unpredictable
3. No clocking mechanism: Cannot synchronize with other digital components
4. Not edge-triggered: Cannot respond to brief pulses reliably
5. Unwanted toggling: May respond to noise or glitches

Table: NAND vs NOR SR Flip-flop

Mnemonic: “NAND: active-low inputs, NOR: active-high inputs; both have an invalid state”

Question 4 [OR Question] (a) [3 marks]

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Write the definition of flip-flop. List the types of flip-flops

Answer:

Flip-flop: A basic sequential digital circuit that can store one bit of information and has two stable states (0 or 1). It serves as a basic memory element in digital systems.

Key characteristics:

• Bistable multivibrator (two stable states)
• Can maintain its state indefinitely until directed to change
• Forms the basic building block for registers, counters, and memory circuits
• Can be triggered by clock signals (synchronous) or level changes (asynchronous)

Types of Flip-flops:

Mnemonic: “Storing a Single Step: SR, JK, D, T”

Question 4 [OR Question] (b) [4 marks]

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Design 3-bit ring counter

Answer:

Ring Counter: A circular shift register where only one bit is set (1) and all others are reset (0). The single set bit “rotates” around the register when clocked.

Design using D flip-flops:

• Requires 3 D flip-flops for 3-bit counter
• Initial state: 100, then cycles through 010, 001, and back to 100

State Table:

Block Diagram:

graph LR
    CLK[Clock] --> FF0[D0]
    CLK --> FF1[D1]
    CLK --> FF2[D2]

    FF0 --Q0--> Q0[Q0]
    FF1 --Q1--> Q1[Q1]
    FF2 --Q2--> Q2[Q2]
    
    Q2 --> FF0
    Q0 --> FF1
    Q1 --> FF2
    
    PRESET[Preset/Clear] -.-> FF0
    PRESET -.-> FF1
    PRESET -.-> FF2

D Input Equations:

• D0 = Q2
• D1 = Q0
• D2 = Q1

Initial state setting: Preset FF0 to 1, Clear FF1 and FF2 to 0

Mnemonic: “One hot bit travels in a circle”

Question 4 [OR Question] (c)(I) [3 marks]

#

Explain J-K flip-flop using its logic symbol and truth table

Answer:

J-K Flip-flop: An improved version of SR flip-flop that eliminates the invalid state and provides predictable behavior in all input combinations.

Logic Symbol:

graph LR
    J[J] --> JK[JK]
    K[K] --> JK
    CLK[Clock] --> JK
    JK --Q--> Q[Q]
    JK --Q'--> Qn[Q']

Truth Table:

Key features:

• When J=K=1, the flip-flop toggles (changes to opposite state)
• No invalid state like in SR flip-flop
• Can perform all operations: Set, Reset, Hold, Toggle

Mnemonic: “J sets, K resets, Both toggle, None remember”

Question 4 [OR Question] (c)(II) [4 marks]

#

Draw logic circuit of D flip-flop and T flip-flop using J-K flip-flop

Answer:

D Flip-flop using JK Flip-flop:

To convert JK to D flip-flop:

• Connect D input to J
• Connect D’ (NOT D) to K

Logic Circuit:

graph LR
    D[D] --> J[J]
    D --> NOT[NOT]
    NOT --> K[K]
    J --> JK[JK Flip-flop]
    K --> JK
    CLK[Clock] --> JK
    JK --Q--> Q[Q]
    JK --Q'--> Qn[Q']

T Flip-flop using JK Flip-flop:

To convert JK to T flip-flop:

• Connect T input to both J and K

Logic Circuit:

graph LR
    T[T] --> J[J]
    T --> K[K]
    J --> JK[JK Flip-flop]
    K --> JK
    CLK[Clock] --> JK
    JK --Q--> Q[Q]
    JK --Q'--> Qn[Q']

Truth Tables:

D Flip-flop:

T Flip-flop:

Mnemonic: “D directly follows, T toggles when true”

Question 5(a) [3 marks]

#

Compare RAM and ROM

Answer:

RAM (Random Access Memory) vs ROM (Read-Only Memory):

Table: RAM vs ROM Comparison

Mnemonic: “RAM Reads And Modifies (but forgets), ROM Remembers On shutdown (but fixed)”

Question 5(b) [4 marks]

#

Explain Serial In Serial Out shift register

Answer:

Serial In Serial Out (SISO) Shift Register: A sequential circuit that shifts data one bit at a time both at input and output.

Operation:

• Data enters serially one bit at a time
• Each bit shifts through the register on each clock pulse
• Data exits serially one bit at a time
• First-in, first-out operation

Block Diagram:

graph LR
    SI[Serial In] --> FF0[D0]
    CLK[Clock] --> FF0
    CLK --> FF1
    CLK --> FF2
    CLK --> FF3

    FF0 --Q0--> FF1[D1]
    FF1 --Q1--> FF2[D2]
    FF2 --Q2--> FF3[D3]
    FF3 --Q3--> SO[Serial Out]

Timing Diagram for shifting “1011”:

CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_
SI    __|‾|_|‾|‾|_________
Q0    ______|‾|_|‾|‾|_____
Q1    ________|‾|_|‾|‾|___
Q2    ____________|‾|_|‾|‾|
SO    ______________|‾|_|‾|

Applications:

• Data transmission between digital systems
• Serial-to-serial data conversion
• Time delay circuits
• Signal filtering

Mnemonic: “Bits enter line, march through chain, exit in sequence”

Question 5(c) [7 marks]

#

Write short note on logic families

Answer:

Logic Families: Groups of digital integrated circuits with similar electrical characteristics, fabrication technology, and logic implementations.

Major Logic Families:

1. TTL (Transistor-Transistor Logic):

   • Based on bipolar junction transistors
   • Standard series: 7400
   • Supply voltage: 5V
   • Moderate speed and power consumption
   • High noise immunity
   • Variants: Standard TTL, Low-power TTL (74L), Schottky TTL (74S), Advanced Schottky (74AS)

2. CMOS (Complementary Metal-Oxide-Semiconductor):

   • Based on MOSFETs (P-type and N-type)
   • Standard series: 4000, 74C00
   • Wide supply voltage range (3-15V)
   • Very low power consumption
   • High noise immunity
   • Susceptible to static electricity
   • Advanced variants: HC, HCT, AC, ACT, AHC, AHCT series

3. ECL (Emitter-Coupled Logic):

   • Based on differential amplifier with emitter-coupled transistors
   • Extremely high speed (fastest logic family)
   • High power consumption
   • Low noise immunity
   • Negative supply voltage
   • Used in high-speed applications

Key Parameters of Logic Families:

Comparison Table:

Mnemonic: “TTL Takes Transistors, CMOS Conserves More Operational Supply, ECL Executes Calculations Lightning-fast”

Question 5 [OR Question] (a) [3 marks]

#

Compare SRAM and DRAM

Answer:

SRAM (Static RAM) vs DRAM (Dynamic RAM):

Table: SRAM vs DRAM Comparison

Mnemonic: “Static Stays steady with Six Transistors, Dynamic Drains and needs regular refreshing”

Question 5 [OR Question] (b) [4 marks]

#

Explain 8:3 encoder

Answer:

8:3 Encoder: A combinational circuit that converts 8 input lines to 3 output lines, essentially converting an active input line to its binary position.

Function:

• Has 8 input lines (I₀ to I₇) and 3 output lines (Y₂, Y₁, Y₀)
• Only one input is active at a time
• Output is the binary code representing position of active input

Logic Circuit:

graph LR
    I1[I1] --> OR0([≥1])
    I3[I3] --> OR0
    I5[I5] --> OR0
    I7[I7] --> OR0
    OR0 --> Y0[Y0]

    I2[I2] --> OR1([≥1])
    I3[I3] --> OR1
    I6[I6] --> OR1
    I7[I7] --> OR1
    OR1 --> Y1[Y1]
    
    I4[I4] --> OR2([≥1])
    I5[I5] --> OR2
    I6[I6] --> OR2
    I7[I7] --> OR2
    OR2 --> Y2[Y2]

Truth Table:

Boolean Equations:

• Y₀ = I₁ + I₃ + I₅ + I₇
• Y₁ = I₂ + I₃ + I₆ + I₇
• Y₂ = I₄ + I₅ + I₆ + I₇

Applications:

• Priority encoders
• Keyboard encoders
• Address decoders
• Data selectors

Mnemonic: “Eight Inputs become their position in Three bits”

Question 5 [OR Question] (c) [7 marks]

#

Define (i) Fan-in (ii) Fan-out (iii) Noise margin (iv) Propagation delay (v) Power dissipation for logic families

Answer:

Key Parameters of Logic Families:

1. Fan-in:

• Definition: Maximum number of inputs a logic gate can accept
• Importance: Determines complexity of logic implementation
• Typical values: 2-8 for most families
• Example: AND gate with 4 inputs has fan-in of 4

2. Fan-out:

• Definition: Maximum number of similar gates that one gate output can drive reliably
• Importance: Determines loading capability and system expandability
• Calculation: Based on output current capacity and input current requirements
• Typical values: TTL: 10, CMOS: 50+, ECL: 25

3. Noise Margin:

• Definition: Measure of circuit’s ability to tolerate unwanted electrical noise/signals
• Importance: Ensures reliable operation in noisy environments
• Calculation: Difference between minimum high output voltage and maximum high input voltage
• Typical values: TTL: 0.4V, CMOS: 1.5V-2.25V, ECL: 0.2V

4. Propagation Delay:

• Definition: Time delay between input change and corresponding output change
• Importance: Determines maximum operating frequency and speed
• Measurement: Time from 50% of input transition to 50% of output transition
• Typical values: TTL: 10ns, CMOS: 5-100ns, ECL: 1-2ns

5. Power Dissipation:

• Definition: Amount of power consumed by a logic gate
• Importance: Affects heat generation, power supply requirements, battery life
• Calculation: Product of supply voltage and current drawn
• Typical values: TTL: 10mW, CMOS: 0.1mW (static), ECL: 25mW

Table: Logic Family Comparison

Diagram: Noise Margin and Switching Thresholds

Voltage
   ^
   |                   VOH
   |    ┌───────┐      │
   |    │       │      │      Logic High
   |    │       │      │
   |    │       │      V      VIH
   |    │       │      │
   |    │  NMH  │      │      Undefined
   |    │       │      │
   |    │       │      V      VIL
   |    │       │      │
   |    │  NML  │      │      Logic Low
   |    │       │      V      VOL
   |    └───────┘
   └─────────────────────────> Signal

Relationships:

• NMH (Noise Margin High) = VOH(min) - VIH(min)
• NML (Noise Margin Low) = VIL(max) - VOL(max)
• Figure of Merit = Power × Delay product (lower is better)

Mnemonic: “Five Factors: Fan-in counts inputs, Fan-out drives gates, Noise margin fights interference, Propagation delay measures speed, Power dissipation generates heat”