Digital Electronics (4321102) - Winter 2024 Solution

Table of Contents

Question 1(a) [3 marks]
#

Draw symbols and write Logic table of NAND and Ex-NOR gate

Answer:

NAND and Ex-NOR Gate Symbols and Truth Tables:

         NAND Gate                 Ex-NOR Gate
         _______                    _______
A --->--|       |                A --->--|       |
        |   &   |-->Y            |   =   |-->Y
B --->--|_______|                B --->--|_______|
        bubble output                 bubble output

A	B	Y (NAND)
0	0	1
0	1	1
1	0	1
1	1	0

A	B	Y (Ex-NOR)
0	0	1
0	1	0
1	0	0
1	1	1

NAND gate: Output is LOW only when all inputs are HIGH
Ex-NOR gate: Output is HIGH when inputs are SAME

Mnemonic: “NAND says NO to ALL ones, Ex-NOR says YES to SAME signals”

Question 1(b) [4 marks]
#

Do as Directed: (i) (1011001)₂ - (1001101)₂ Using 2’s Complement (ii) (10110101)₂ = ( )₁₀ = ( )₁₆

Answer:

(i) Subtraction using 2’s complement:

Step 1: Find 2's complement of subtrahend (1001101)₂
        1's complement: 0110010
        Add 1:          0110011

Step 2: Add minuend and 2's complement
        1011001
      + 0110011
        -------
       10001100

Step 3: Discard overflow bit
        Result = 0001100 = (0001100)₂

(ii) Conversion of (10110101)₂:

To Decimal:
1×2⁷ + 0×2⁶ + 1×2⁵ + 1×2⁴ + 0×2³ + 1×2² + 0×2¹ + 1×2⁰
= 128 + 0 + 32 + 16 + 0 + 4 + 0 + 1
= 181₁₀

To Hexadecimal:
1011 0101
 B    5
= B5₁₆

2’s complement: Invert bits and add 1
Binary to decimal: Multiply each bit by its position value (2ⁿ)
Binary to hex: Group bits in fours, convert each group

Mnemonic: “Flip bits Add 1, Drop the carry”

Question 1(c) [7 marks]
#

Find (i) (4356)₁₀ = ( )₈ = ( )₁₆ = ()₂ (ii) (101.01)₂ × (11.01)₂ (iii) Divide (101101)₂ with (110)₂

Answer:

(i) Number system conversion:

Decimal to Octal:
4356 ÷ 8 = 544 remainder 4
544 ÷ 8 = 68  remainder 0
68 ÷ 8 = 8    remainder 4
8 ÷ 8 = 1     remainder 0
1 ÷ 8 = 0     remainder 1
Reading from bottom: (4356)₁₀ = (10404)₈

Decimal to Hexadecimal:
4356 ÷ 16 = 272 remainder 4
272 ÷ 16 = 17  remainder 0
17 ÷ 16 = 1    remainder 1
1 ÷ 16 = 0     remainder 1
Reading from bottom: (4356)₁₀ = (1104)₁₆

Decimal to Binary:
4356 = 1000100000100₂

(ii) Binary multiplication:

(iii) Binary division:

          111.
       ------
110 ) 101101
      110
      -----
       11101
       110
       -----
       1001
        110
        ----
        11

Decimal to Octal: Divide repeatedly by 8
Decimal to Hex: Divide repeatedly by 16
Binary operations: Follow same process as decimal

Mnemonic: “Divide and stack up the remainders from bottom to top”

Question 1(c-OR) [7 marks]
#

Find (i) (8642)₁₀ = ( )₈ = ( )₁₆ = ()₂ (ii) Draw symbols and write Logic table of NOR and Ex-OR gate

Answer:

(i) Number system conversion:

Decimal to Octal:
8642 ÷ 8 = 1080 remainder 2
1080 ÷ 8 = 135  remainder 0
135 ÷ 8 = 16    remainder 7
16 ÷ 8 = 2      remainder 0
2 ÷ 8 = 0       remainder 2
Reading from bottom: (8642)₁₀ = (20702)₈

Decimal to Hexadecimal:
8642 ÷ 16 = 540 remainder 2
540 ÷ 16 = 33   remainder 12(C)
33 ÷ 16 = 2     remainder 1
2 ÷ 16 = 0      remainder 2
Reading from bottom: (8642)₁₀ = (21C2)₁₆

Decimal to Binary:
8642 = 10000111000010₂

(ii) NOR and Ex-OR Gates:

         NOR Gate                 Ex-OR Gate
         _______                    _______
A --->--|       |                A --->--|       |
        |  ≥1   |-->Y            |   =   |-->Y
B --->--|_______|                B --->--|_______|
         bubble output

A	B	Y (NOR)
0	0	1
0	1	0
1	0	0
1	1	0

A	B	Y (Ex-OR)
0	0	0
0	1	1
1	0	1
1	1	0

NOR gate: Output is HIGH only when ALL inputs are LOW
Ex-OR gate: Output is HIGH when inputs are DIFFERENT

Mnemonic: “NOR says YES to ALL zeros, Ex-OR says YES to DIFFERENT signals”

Question 2(a) [3 marks]
#

Prove xy+xz+yz’ = xz+yz’

Answer:

Left side: xy + xz + yz'
= xy + xz + yz'
= x(y + z) + yz'        [Distributive property]
= xy + xz + yz'         [Expand]
= xy + yz' + xz         [Rearranging]
= y(x + z') + xz        [Distributive property]
= xy + yz' + xz         [Expand]
= (x + y)z' + xz        [Rearranging]
= xz' + yz' + xz        [Expand]
= x(z' + z) + yz'       [Distributive property]
= x(1) + yz'            [Complement property]
= x + yz'               [Identity property]
= xz + x(1-z) + yz'     [x = xz + xz']
= xz + xz' + yz'        [Expand]
= xz + z'(x + y)        [Distributive property]
= xz + z'x + z'y        [Expand]
= xz + xz' + yz'        [Rearranging]
= x(z + z') + yz'       [Distributive property]
= x(1) + yz'            [Complement property]
= x + yz'               [Identity property]
= xz + yz'              [Same as right side]

Distributive property: x(y+z) = xy+xz
Complement property: z+z’ = 1
Identity property: x×1 = x

Mnemonic: “Factor, Expand, Rearrange, Factor again”

Question 2(b) [4 marks]
#

Reduce Expression f(W,X,Y,Z) = ∑m(0,1,2,3,5,7,8,9,11,14) using K-Map method.

Answer:

K-Map for f(W,X,Y,Z) = ∑m(0,1,2,3,5,7,8,9,11,14):

      YZ
WX   00  01  11  10
00    1   1   0   1
01    1   1   1   0
11    0   0   1   1
10    1   1   0   0

Grouping:

Group 1: m(0,1,2,3) = W’X’ (2×2 group)
Group 2: m(0,1,8,9) = Y’ (2×2 group)
Group 3: m(2,3,11) = X’Z (2×2 group with wrapping)
Group 4: m(7,14) = XZ (pair)

Simplified expression: f(W,X,Y,Z) = W’X’ + Y’ + X’Z + XZ

K-Map technique: Group adjacent 1’s in powers of 2
Each group: Represents one term in simplified expression
Larger groups: Mean simpler expressions

Mnemonic: “Powers of 2 make expressions new”

Question 2(c) [7 marks]
#

Explain NOR gate as Universal Gate

Answer:

NOR as Universal Gate:

NOR gate can implement all basic logic functions, making it a universal gate.

Implementation of basic gates using NOR:

Gate	Implementation with NOR
NOT	A NOR A
OR	(A NOR B) NOR (A NOR B)
AND	(A NOR A) NOR (B NOR B)

Circuit diagrams:

NOT Gate using NOR:
A--->|NOR|-->Y

OR Gate using NOR:
A--->|     |      |     |
     | NOR |------|     |
B--->|     |      | NOR |-->Y
                  |     |
                  |     |

AND Gate using NOR:
A--->|NOR|------|     |
                 |     |
                 | NOR |-->Y
                 |     |
B--->|NOR|------|     |

Universal gate: Can implement any Boolean function
NOR operation: NOT OR, output high only when all inputs low
Implementation cost: Requires multiple NOR gates for complex functions

Mnemonic: “NOR stands for Not-OR, but can do Not-AND-OR all”

Question 2(a-OR) [3 marks]
#

Draw Logic circuit for Boolean expression P = (x’+y’+z)(x+y+z’)+(xyz)

Answer:

Logic Circuit for P = (x’+y’+z)(x+y+z’)+(xyz):

       |------|
x'--->|      |
y'--->| OR   |-----|
z---->|      |     |     |------|
       |------|     |---->|      |
                          | AND  |------|
       |------|     |---->|      |      |
x---->|      |     |      |------|      |     |------|
y---->| OR   |-----|                    |---->|      |
z'--->|      |                          |     | OR   |---> P
       |------|                         |     |      |
                                        |     |------|
       |------|                         |
x---->|      |                         |
y---->| AND  |-------------------------|
z---->|      |
       |------|

Step 1: Implement each product term
Step 2: Then combine with OR gate
Step 3: Follow operator precedence

Mnemonic: “Products first, then sum them up”

Question 2(b-OR) [4 marks]
#

Reduce Expression using K-Map method f(W,X,Y,Z) = ∑m(1,3,7,11,15) and don’t care condition are d(0,2,5)

Answer:

K-Map with don’t care conditions:

      YZ
WX   00  01  11  10
00    d   1   0   d
01    0   0   1   d
11    0   0   1   1
10    0   0   1   0

Grouping:

Group 1: m(1,3,7,15) + d(0,2) = X’Z + YZ (pairs)
Group 2: m(7,15) + d(5) = WYZ (quad)

Simplified expression: f(W,X,Y,Z) = X’Z + YZ

Don’t care conditions: Can be treated as 0 or 1 based on convenience
Optimal grouping: Use don’t cares to form larger groups
Simplification goal: Minimize number of terms

Mnemonic: “Don’t cares help make bigger squares”

Question 2(c-OR) [7 marks]
#

Write Basic Boolean Theorem and its all Properties.

Answer:

Basic Boolean Theorems and Properties:

Law/Property	Expression
Identity Law	A + 0 = A, A · 1 = A
Null Law	A + 1 = 1, A · 0 = 0
Idempotent Law	A + A = A, A · A = A
Complementary Law	A + A’ = 1, A · A’ = 0
Commutative Law	A + B = B + A, A · B = B · A
Associative Law	A + (B + C) = (A + B) + C, A · (B · C) = (A · B) · C
Distributive Law	A · (B + C) = A · B + A · C, A + (B · C) = (A + B) · (A + C)
Absorption Law	A + (A · B) = A, A · (A + B) = A
DeMorgan’s Theorem	(A + B)’ = A’ · B’, (A · B)’ = A’ + B'
Double Complement	(A’)’ = A
Consensus Theorem	(A · B) + (A’ · C) + (B · C) = (A · B) + (A’ · C)

Basic operations: AND (·), OR (+), NOT (')
Key applications: Circuit simplification and design
Theorem importance: Reduces gate count and complexity

Mnemonic: “COIN-CADDAM” (Complementary, Distributive, Associative, etc.)

Question 3(a) [3 marks]
#

Draw the Logic circuit of Full substractor and explain its working.

Answer:

Full Subtractor Circuit:

          |------|
A-------->|      |
          | XOR  |---------|
B-------->|      |         |     |------|
          |------|         |---->|      |
                                 | XOR  |---> Difference
          |------|         |---->|      |
C_in---->|      |         |     |------|
         |      |---------|
A------->| NAND |
         |      |
          |------|                |------|
                                 |      |---> Borrow
          |------|         |---->| OR   |
B-------->|      |         |     |      |
          | NAND |---------|     |------|
C_in---->|      |
          |------|

Truth Table:

A	B	C_in	Difference	Borrow
0	0	0	0	0
0	0	1	1	1
0	1	0	1	1
0	1	1	0	1
1	0	0	1	0
1	0	1	0	0
1	1	0	0	0
1	1	1	1	1

Difference: A ⊕ B ⊕ C_in (XOR of all inputs)
Borrow: C_in·(A ⊕ B) + B·A’ (generated when needed)

Mnemonic: “Borrow is needed when subtrahend exceeds minuend”

Question 3(b) [4 marks]
#

Draw the circuit of Gray to binary code converter.

Answer:

Gray to Binary Code Converter (4-bit):

       G3          G2          G1          G0
       |           |           |           |
       |           |           |           |
       v           v           v           v
       |------|    |------|    |------|    |
       |      |    |      |    |      |    |
G3---->| XNOR |--->| XNOR |--->| XNOR |--->|--> B0
       |      |    |      |    |      |    |
       |------|    |------|    |------|    |
         ^           ^           ^         |
         |           |           |         |
       B3 |        B2 |        B1 |        G0=B0

Conversion Table:

Gray	Binary
G3G2G1G0	B3B2B1B0
0000	0000
0001	0001
0011	0010
0010	0011
0110	0100
…	…

Conversion principle: B₃ = G₃, B₂ = B₃ ⊕ G₂, B₁ = B₂ ⊕ G₁, B₀ = B₁ ⊕ G₀
Key feature: Each binary bit depends on all previous gray bits
Application: Error detection in digital transmission

Mnemonic: “MSB stays, others XOR with previous binary”

Question 3(c) [7 marks]
#

Draw and explain 2:4 Decoder and 4:1 Multiplexer and explain its working.

Answer:

2:4 Decoder:

       |------|
       |      |-----> Y0 (A'B')
       |      |
A----->| 2:4  |-----> Y1 (A'B)
       |      |
B----->| DEC  |-----> Y2 (AB')
       |      |
       |      |-----> Y3 (AB)
       |------|

Truth Table:

A	B	Y0	Y1	Y2	Y3
0	0	1	0	0	0
0	1	0	1	0	0
1	0	0	0	1	0
1	1	0	0	0	1

4:1 Multiplexer:

       |------|
D0---->|      |
       |      |
D1---->| 4:1  |
       |      |-----> Y
D2---->| MUX  |
       |      |
D3---->|      |
       |------|
         ^  ^
         |  |
        S0 S1

Truth Table:

S1	S0	Y
0	0	D0
0	1	D1
1	0	D2
1	1	D3

Decoder: Converts binary code to one-hot output
Multiplexer: Selects one of many inputs based on selection lines
Applications: Memory addressing, data routing

Mnemonic: “Decoder: One-to-Many, Mux: Many-to-One”

Question 3(a-OR) [3 marks]
#

Draw the Logic circuit of full adder and explain its working.

Answer:

Full Adder Circuit:

          |------|
A-------->|      |
          | XOR  |---------|
B-------->|      |         |     |------|
          |------|         |---->|      |
                                 | XOR  |---> Sum
          |------|         |---->|      |
C_in---->|      |         |     |------|
         |      |---------|
         |      |
          |------|
                          |------|
          |------|        |      |
A-------->|      |------->|      |
          | AND  |        |      |
B-------->|      |        |  OR  |---> Carry
          |------|        |      |
                          |      |
          |------|        |      |
C_in---->|      |------->|      |
         | AND  |        |------|
XOR---->|      |
          |------|

Truth Table:

A	B	C_in	Sum	Carry
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

Sum: A ⊕ B ⊕ C_in (XOR of all inputs)
Carry: (A · B) + (C_in · (A ⊕ B)) (generated when needed)

Mnemonic: “Sum is odd, Carry needs at least two 1’s”

Question 3(b-OR) [4 marks]
#

Draw the circuit of Binary to gray code converter.

Answer:

Binary to Gray Code Converter (4-bit):

      B3          B2          B1          B0
       |           |           |           |
       |           |           |           |
       v           v           v           v
       |------|    |------|    |------|    |
       |      |    |      |    |      |    |
B3---->|      |--->|      |--->|      |--->|--> G0
       | XOR  |    | XOR  |    | XOR  |    |
       |------|    |------|    |------|    |
         ^           ^           ^         |
         |           |           |         |
        B2          B1          B0         |
                                           |
       |                                   |
       v                                   v
       G3                                  G0

Conversion Table:

Binary	Gray
B3B2B1B0	G3G2G1G0
0000	0000
0001	0001
0010	0011
0011	0010
0100	0110
…	…

Conversion principle: G₃ = B₃, G₂ = B₃ ⊕ B₂, G₁ = B₂ ⊕ B₁, G₀ = B₁ ⊕ B₀
Key feature: Only one bit changes between adjacent codes
Application: Rotary encoders, error detection

Mnemonic: “MSB stays, others XOR adjacent binary bits”

Question 3(c-OR) [7 marks]
#

Draw the logic diagram of 4 bit parallel adder using full adder and explain its working.

Answer:

4-bit Parallel Adder using Full Adders:

A3    B3      A2    B2      A1    B1      A0    B0
 |     |       |     |       |     |       |     |
 v     v       v     v       v     v       v     v
|---------|  |---------|  |---------|  |---------|
|         |  |         |  |         |  |         |
|   FA    |  |   FA    |  |   FA    |  |   FA    |
|         |  |         |  |         |  |         |
|---------|  |---------|  |---------|  |---------|
     |            |            |            |
     v            v            v            v
    S3           S2           S1           S0
     
     ^            ^            ^            ^
     |            |            |            |
C_out         C3           C2           C1      C_in=0

Operation:

Each Full Adder (FA) adds corresponding bits (Ai, Bi) plus carry from previous stage
Produces Sum (Si) and Carry (Ci+1) for next stage
C_in of first FA is 0 (or can be 1 for adding 1)
C_out of last FA indicates overflow

Example Addition: 1101 + 1011

A₃A₂A₁A₀ = 1101
B₃B₂B₁B₀ = 1011
C_in = 0
S₃S₂S₁S₀ = 1000
C_out = 1 (indicating overflow, actual result is 11000)
Parallel adder: Adds multiple bits simultaneously
Carry propagation: Key limiting factor for speed
Adder applications: ALU, address calculation

Mnemonic: “Carries cascade from right to left”

Question 4(a) [3 marks]
#

Draw the Diagram of BCD counter

Answer:

BCD Counter Diagram:

       |------|    |------|    |------|    |------|
       |      |    |      |    |      |    |      |
CLK--->| JK-FF|--->| JK-FF|--->| JK-FF|--->| JK-FF|
       |  Q0  |    |  Q1  |    |  Q2  |    |  Q3  |
       |------|    |------|    |------|    |------|
          |           |           |           |
          v           v           v           v
         Q0          Q1          Q2          Q3
          |           |           |           |
          |-----------|-----------|-----------|
                            |
                            v
                        |------|
                        | NAND |----+
                        |------|    |
                                    |
                                    v
                                  RESET

Counter Sequence:

Count	Q3	Q2	Q1	Q0
0	0	0	0	0
1	0	0	0	1
2	0	0	1	0
3	0	0	1	1
4	0	1	0	0
5	0	1	0	1
6	0	1	1	0
7	0	1	1	1
8	1	0	0	0
9	1	0	0	1
0	0	0	0	0

BCD counter: Counts from 0 to 9, then resets
Reset mechanism: Detects count of 10 (1010) and resets to 0
Applications: Digital clocks, frequency counters

Mnemonic: “Counts Decimal Digits Only (0-9)”

Question 4(b) [4 marks]
#

Draw T flip flop diagram and explain its working with truth table

Answer:

T Flip-Flop Diagram:

       |------|
       |      |
T----->|      |
       |  T   |
CLK--->|  FF  |-----> Q
       |      |
       |      |-----> Q'
       |------|

Implementation using JK Flip-Flop:

       |------|
       |      |
T----->| J    |
       |      |
       | JK   |-----> Q
CLK--->|      |
       | FF   |-----> Q'
       |      |
T----->| K    |
       |------|

Truth Table:

T	CLK	Q(next)
0	↑	Q
1	↑	Q'

T=0: No change in output (Hold)
T=1: Output toggles (Complement)
Toggle operation: Changes state on each clock pulse when T=1

Mnemonic: “T for Toggle, 0 holds 1 flips”

Question 4(c) [7 marks]
#

What is shift register? Lists different types of shift register. Explain working of any one type shift register with its logic circuit.

Answer:

Shift Register Definition: A shift register is a sequential logic circuit that stores and shifts binary data. It consists of a series of flip-flops where the output of one flip-flop becomes input to the next.

Types of Shift Registers:

Type	Description
SISO	Serial Input Serial Output
SIPO	Serial Input Parallel Output
PISO	Parallel Input Serial Output
PIPO	Parallel Input Parallel Output
Bidirectional	Can shift in either direction
Ring Counter	Output of last stage fed to first stage
Johnson Counter	Complement of last stage fed to first stage

Serial-In Serial-Out (SISO) Shift Register:

      |------|    |------|    |------|    |------|
      |      |    |      |    |      |    |      |
IN--->| D FF |--->| D FF |--->| D FF |--->| D FF |---> OUT
      |      |    |      |    |      |    |      |
      |------|    |------|    |------|    |------|
         ^          ^          ^          ^
         |          |          |          |
         |----------|----------|----------|
                       CLK

Operation:

Data enters serially bit by bit through the input
With each clock pulse, data shifts one position to the right
After 4 clock pulses, the first input bit appears at the output
Example: For input “1101”, need 4 clock pulses for complete transmission

Primary use: Data conversion between serial and parallel formats
Applications: Communication systems, data transfer between devices
Advantages: Simple design, minimal interconnections

Mnemonic: “Shift registers pass bits like a bucket brigade”

Question 4(a-OR) [3 marks]
#

Draw and Explain 4:2 Encoder.

Answer:

4:2 Encoder Diagram:

      |------|
D0--->|      |
      |      |---> A
D1--->|      |
      | 4:2  |
D2--->|      |
      |      |---> B
D3--->|      |
      |------|

Truth Table:

D3	D2	D1	D0	B	A
0	0	0	1	0	0
0	0	1	0	0	1
0	1	0	0	1	0
1	0	0	0	1	1

Logical Expressions:

A = D1 + D3
B = D2 + D3
Encoder function: Converts one-hot input to binary code
Priority encoders: Handle multiple active inputs by priority
Applications: Keyboard scanning, interrupt handling

Mnemonic: “One active line IN, binary code OUT”

Question 4(b-OR) [4 marks]
#

Draw and explain Johnson counter.

Answer:

Johnson Counter (4-bit):

    |------|    |------|    |------|    |------|
    |      |    |      |    |      |    |      |
    | D FF |----| D FF |----| D FF |----| D FF |
    |      |    |      |    |      |    |      |
    |------|    |------|    |------|    |------|
       ^          ^          ^          ^
       |          |          |          |
       |----------|----------|----------|
                    CLK
               |
        Q3'    |
         |     |
         |     v
         ----->|

Counter Sequence:

Count	Q3	Q2	Q1	Q0
0	0	0	0	0
1	1	0	0	0
2	1	1	0	0
3	1	1	1	0
4	1	1	1	1
5	0	1	1	1
6	0	0	1	1
7	0	0	0	1
0	0	0	0	0

Johnson counter: Also called twisted ring counter
Sequence length: 2n states where n is number of flip-flops
Key feature: Only one bit changes between adjacent states

Mnemonic: “Fill with 1’s then clear with 0’s”

Question 4(c-OR) [7 marks]
#

Draw and explain 4 bit Ripple counter.

Answer:

4-bit Ripple Counter:

         CLK
          |
          v
       |------|    |------|    |------|    |------|
       |      |    |      |    |      |    |      |
------>| T FF |    | T FF |    | T FF |    | T FF |
       |      |    |      |    |      |    |      |
       |------|    |------|    |------|    |------|
          |           |           |           |
          |           |           |           |
         Q0 --------->Q1 -------->Q2 -------->Q3
       (LSB)                                 (MSB)

Truth Table (Counting Sequence):

Count	Q3	Q2	Q1	Q0
0	0	0	0	0
1	0	0	0	1
2	0	0	1	0
3	0	0	1	1
…	..	..	..	..
14	1	1	1	0
15	1	1	1	1
0	0	0	0	0

Working Principle:

All T inputs are connected to logic 1 (toggle mode)
First flip-flop toggles on every clock pulse
Each subsequent flip-flop toggles when the previous one changes from 1 to 0
Propagation delay increases with each stage

Asynchronous counter: Clock drives only first flip-flop
Ripple effect: Changes propagate through stages
Disadvantage: Slower due to cumulative propagation delays

Mnemonic: “Change ripples through like falling dominoes”

Question 5(a) [3 marks]
#

Explain DRAM in short.

Answer:

Dynamic Random Access Memory (DRAM):

DRAM is a type of semiconductor memory that stores each bit in a separate capacitor.

Key Features:

Feature	Description
Storage element	Single capacitor + transistor per bit
Density	Very high (more bits per chip)
Speed	Moderate (slower than SRAM)
Refresh	Required periodically (typically every few ms)
Power consumption	Lower than SRAM
Cost	Less expensive than SRAM

Dynamic nature: Charge leaks over time, requiring refresh
Applications: Main memory in computers
Advantage: High density, low cost per bit

Mnemonic: “DRAM needs refreshing like a tired mind”

Question 5(b) [4 marks]
#

Define the following (1) Fan in (2) Propagation Delay

Answer:

Fan-in:

Fan-in refers to the maximum number of inputs that a logic gate can accept.

Characteristics of Fan-in:

Measures input load capability
Affects circuit complexity and design
Higher fan-in reduces gate count but increases complexity
Different logic families have different fan-in limits

Example: A standard TTL NAND gate typically has a fan-in of 8 inputs.

Propagation Delay:

Propagation delay is the time taken for a signal to travel from input to output of a logic gate.

Characteristics of Propagation Delay:

Measured in nanoseconds (ns)
Critical for high-speed circuit performance
Varies with temperature, loading, and supply voltage
Different for rising and falling transitions

Example: A typical TTL gate has a propagation delay of 10-20 ns.

Impact on circuits: Limits maximum operating frequency
Calculation: Time between 50% points of input and output signals

Mnemonic: “Fan-in counts inputs, Prop-delay counts time”

Question 5(c) [7 marks]
#

Do as Directed (i) Compare Logic families TTL and CMOS (ii) Draw Circuit Diagram of SR flip flop.

Answer:

(i) Comparison of TTL and CMOS Logic Families:

Parameter	TTL	CMOS
Technology	Bipolar transistors	MOSFETs
Supply voltage	5V (fixed)	3-15V (flexible)
Power consumption	Higher	Very low (static)
Speed	Medium to high	Low to very high
Noise margin	Moderate	High
Fan-out	10-20	>50
Propagation delay	5-10 ns	10-100 ns (standard)
Input impedance	4-40 kΩ	Very high (10¹² Ω)
Output impedance	100-300 Ω	Variable
Susceptibility to static	Low	High

(ii) SR Flip-Flop Circuit Diagram:

             |------|
             |      |
Set -------->|      |-----> Q
             | NOR  |
             |      |
             |------|
                ^
                |
                |    |------|
                |    |      |
                |----|      |-----> Q'
                     | NOR  |
                     |      |
Reset ------------->|      |
                     |------|

Truth Table:

S	R	Q	Q'	Remarks
0	0	Q	Q'	Memory (no change)
0	1	0	1	Reset
1	0	1	0	Set
1	1	0	0	Invalid (avoid)

SR flip-flop: Basic memory element in digital circuits
Operation: Set (S=1, R=0) makes Q=1; Reset (S=0, R=1) makes Q=0
Memory state: When S=0, R=0, output remains unchanged

Mnemonic: “SR: Set-Reset, memory when both low”

Question 5(a-OR) [3 marks]
#

Write short note on E Waste of Digital Chips.

Answer:

E-Waste of Digital Chips:

E-waste from digital chips refers to discarded electronic devices containing semiconductor components that require special handling and disposal.

Key Concerns:

Aspect	Details
Hazardous materials	Lead, mercury, cadmium, brominated flame retardants
Environmental impact	Soil and water contamination if improperly disposed
Resource recovery	Contains valuable metals (gold, silver, copper)
Volume	Growing rapidly with technological advancement
Regulations	Governed by WEEE, RoHS directives in many countries

Management Approaches:

Recycling through authorized e-waste handlers
Recovery of precious metals
Safe disposal of toxic components
Extended producer responsibility programs
Challenges: Informal recycling causing health hazards
Solutions: Design for disassembly, green manufacturing

Mnemonic: “Digital waste needs digital-age solutions”

Question 5(b-OR) [4 marks]
#

Define the following (1) Fan out (2) Noise margin

Answer:

Fan-out:

Fan-out is the maximum number of gate inputs that can be driven by a single logic gate output while maintaining proper logic levels.

Characteristics of Fan-out:

Measures output drive capability
Affects design flexibility and cost
Higher fan-out allows simpler wiring
Limited by current sourcing/sinking capacity

Example: A standard TTL gate has a fan-out of 10, meaning it can drive 10 similar gates.

Noise Margin:

Noise margin is the amount of noise voltage that can be added to an input signal without causing an undesired change in the circuit output.

Characteristics of Noise Margin:

Expressed in volts
Measures circuit immunity to electrical noise
Higher noise margin means more reliable operation
Different for high and low logic levels

Example: TTL has noise margins of approximately 0.4V for logic low and 0.7V for logic high.

Calculation: Difference between guaranteed output and required input levels
Importance: Critical in electrically noisy environments

Mnemonic: “Fan-out counts outputs, Noise margin fights interference”

Question 5(c-OR) [7 marks]
#

Do as Directed (i) Write short note on ROM (ii) Explain JK master slave flipflop.

Answer:

(i) Short Note on ROM:

ROM (Read-Only Memory) is a non-volatile memory used to store permanent or semi-permanent data.

Types of ROM:

Type	Characteristics	Programming
Mask ROM	Factory programmed	During manufacturing
PROM	One-time programmable	Electrical fusing by user
EPROM	Erasable with UV light	Electrical programming
EEPROM	Electrically erasable	Electrical programming/erasing
Flash ROM	Fast electrical erase	Block-wise erase/write

Applications:

Firmware and BIOS storage
Look-up tables for fixed functions
Microcode in processors
Boot code in computers
Data retention: Maintains data without power
Access time: Typically 45-150 ns
Density: High storage capacity

(ii) JK Master-Slave Flip-Flop:

         |-----------|        |-----------|
         |           |        |           |
J ------>|           |        |           |-----> Q
         |  Master   |------->|   Slave   |
K ------>|           |        |           |-----> Q'
         |           |        |           |
         |-----------|        |-----------|
               ^                    ^
               |                    |
         CLK --|                 INV|-- CLK

Truth Table:

J	K	Q(next)	Function
0	0	Q	No change
0	1	0	Reset
1	0	1	Set
1	1	Q'	Toggle

Operation:

Master stage: When CLK=1, master latch samples J and K inputs
Slave stage: When CLK=0, slave latch samples master output
Two-phase operation: Prevents race condition (changes occur only on clock edge)
Advantage: More versatile than SR flip-flop (no invalid state)

Toggle mode: When J=K=1, output toggles on each clock cycle
Applications: Counters, shift registers, sequential circuits

Mnemonic: “J-K: Set-Reset-Toggle, Master leads Slave follows”